The weak inversion bulk-transconductance (g mb) is given as g m b = I B P 1 / n p U Twhere n p is subslope factor of PMOS transistor and U T is thermal voltage 25.6 mV at ambient temperature (300 K). The aspect ratios of the combiner network are set to ensure required values of symmetric positive and negative SR. The total current flowing in N 1 or N 2 is the sum of the drain current of P 1 or P 2 and the current coming from the up-side circuit portion (say N 3 or N 4) of its combiner network.
The circuit is simulated using PMOS input pair because the flicker noise of PMOS devices is less than NMOS devices, and the bulk of PMOS devices are only available in n-tub process. The current through the input pairs P 1 and P 2 is obtained as 90.66 nA. The folded cascode combiner network consists of two NMOS cascode pairs N 1, N 3 and N 2, N 4 as well as two-PMOS cascode pairs P 4, P 6 and P 5, P7 (see Fig. 13.2).
The tail PMOS transistor P 3 generates a current of 182.3 nA for PMOS input pair transistors P 1 and P 2. This circuit is biased in weak inversion region using I B of 18 nA and CMOS transistors N B1 through N B4 and P B1 through P B3 to generate required gate-bias reference voltages of V BN1, V BN2, and V BP1.
